Size reduction of metal-oxide-semiconductor field-effect transistors (MOSFETs), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. To further enhance transistor performance, MOSFET devices have been fabricated using strained channel regions located in portions of a semiconductor substrate. Strained channel regions allow enhanced carrier mobility to be realized, thereby resulting in increased performance when used for n-channel (NMOSFET) or for p-channel (PMOSFET) devices. Generally, it is desirable to induce a tensile strain in the n-channel of an NMOSFET transistor in the source-to-drain direction to increase electron mobility and to induce a compressive strain in the p-channel of a PMOSFET transistor in the source-to-drain direction to increase hole mobility. There are several existing approaches of introducing strain in the transistor channel region.
In one approach, semiconductor alloy layers, such as silicon-germanium or silicon-germanium-carbon, are formed below an overlying thin semiconductor layer, wherein the semiconductor alloy layer has a different lattice structure than the overlying semiconductor layer. The difference in the lattice structure imparts strain in the overlying semiconductor layer to increase carrier mobility.
This approach, however, can be difficult to process in addition to presenting junction leakage concerns as a result of the blanket semiconductor alloy layer. The level of germanium in the epitaxially grown semiconductor alloy layer can be difficult to control. In addition, the presence of a blanket semiconductor alloy layer allows an unwanted interface between the source/drain regions to exist, possibly introducing junction leakage.
In another approach, strain in the channel is introduced by creating a recess in the substrate in the source/drain regions. A layer of SiGe is epitaxially grown within the recessed regions, thereby introducing strain in the channel. The amount of stress may be increased by increasing the Ge concentration during the growth process. To increase the Ge concentration in the recessed area, however, creates process challenges. For example, increasing the Ge concentration during the epitaxial growth results in a higher density of dislocations and defects in the SiGe layer. Degraded selectivity and deposition process windows are also of concern.
Therefore, there is a need for an efficient and cost-effective method to induce strain in the channel region such that the performance characteristics of transistors are enhanced.